8Mb Dual Port
Synch. RH-SRAM
C035HS512K16 - 8Mb Dual Port Synchronous RH-SRAM (preliminary)
C035HS512K16 is a high performance, synchronous Dual Port 8Mb RH-SRAM organized as 524,288 words by 16 bits. It is pin selectable: master or slave. The master device is a full function device with user defined autonomous EDAC and scrub options. The slave device employs a scrub on demand feature that can be initiated by a master device. The C035HS512K16 is manufactured by Texas Instruments using HardSIL™ technology from SST.
Features
Synch. RH-SRAM
C035HS512K16 - 8Mb Dual Port Synchronous RH-SRAM (preliminary)
C035HS512K16 is a high performance, synchronous Dual Port 8Mb RH-SRAM organized as 524,288 words by 16 bits. It is pin selectable: master or slave. The master device is a full function device with user defined autonomous EDAC and scrub options. The slave device employs a scrub on demand feature that can be initiated by a master device. The C035HS512K16 is manufactured by Texas Instruments using HardSIL™ technology from SST.
Features
- Access time: <20ns flow through mode, <10ns pipeline mode
- Selectable between flow through and pipeline modes
- Built-in Error Detection and Correction (EDAC) to mitigate soft errors
- Built-in scrub engine for autonomous correction
- Built-in address counter for sequential memory access with repeat feature
- Dual chip enable allows for depth and width expansion without additional logic
- Asynchronous output enable for each port
- Support various clock modes and stress test modes
- CMOS compatible input and output level, three state bidirectional data bus
- 3.3 +/- 0.3V I/O, 1.5 +/- 0.15V CORE
- Packaging options: 128-lead ceramic quad flatpack (CQFP128)
- TID immunity: >300krad (Si)
- SER: <5e-17 upsets/bit-day (core using ECC and Scrub) calculated using CREME96 for geosynchronous orbit, solar minimum
- Latch-up immunity: >LET 110 MeV (T=398K)